SR-71-A Power setting

[cgervasi]

I am not able to get the SR-71-A's power beyond 18dBm. It increases nicely from 0 to 18dBm, but it won't go any higher. The problem may be in our software vendor's code, but I was hoping someone could give me any tricks to pass along to them to get the power up.

I imagine the Atheros reference design isn't for high power. Are there any Ubiquiti-specific registers that control high power operation?

Thanks!

CJ

[UBNT-Mike.Ford]

Hello,

What software are you using and do they take into account our power offset?

Thanks,

Mike

[cgervasi]

The software is based on Linux. What do they need to do to account for the power offset?

Thanks,

CJ

[UBNT-Mike.Ford]

Hello,

Most of the time the Linux software out there will set the target power (18) and our cards apply an offset through the EEPROM to achieve the maximum ouptut for our particular card.

Thanks,

Mike

[rajendra]

Hello,

We are the software vendor which Charles mentioned in the first post and here are the more details on the issue:

We are using atheros 11N linux driver and the function which determines the TX power is exactly same as the ar5416SetPowerPerRateTable function http://ftp.netbsd.org/pub/NetBSD/NetBSD-current/src/sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c.

What we are seeing is that function starts with maxRegulatoryPower (27 dBm for channel 2) and starts reducing it based on the number of TX chains and CTL indexes stored in the EEPROM and is ending up with 18 dBm.

I have pasted some driver debug output at the end which shows how it is coming up with 18 dBm. The number of TX chains is something we can control but it is consulting the CTL indexes in the EEPROM after which it is reducing the power. Is something wrong with the EEPROM settings or driver is not doing it correctly ?

Thanks,

rajendra

output from ar5416SetPowerPerRateTable()
=====================================
twiceLargestAntenna=0 twiceMaxRegulatoryPower=54 tpscale=0 reduction=0 powlimit=62 scaledpower=54 chains=3

LOOP-Mode ctlMode 0 < 3, isHt40CtlMode 0, EXT_ADDITIVE 0
LOOP-Ctlidx 0: cfgCtl 0x12 pCtlMode 0x01 ctlIndex 0x10 chan 2417 chanctl 0x12
LOOP-Ctlidx 1: cfgCtl 0x12 pCtlMode 0x01 ctlIndex 0x16 chan 2417 chanctl 0x12
LOOP-Ctlidx 2: cfgCtl 0x12 pCtlMode 0x01 ctlIndex 0x18 chan 2417 chanctl 0x12
LOOP-Ctlidx 3: cfgCtl 0x12 pCtlMode 0x01 ctlIndex 0x11 chan 2417 chanctl 0x12
MATCH-EE_IDX 3: ch 2417 is2 1 2xMinEdge 38 chainmask 7 chains 3
SEL-Min ctlMode 0 pCtlMode 1 2xMaxEdge 38 sP 44 minCtlPwr 38
LOOP-Mode ctlMode 1 < 3, isHt40CtlMode 0, EXT_ADDITIVE 0
LOOP-Ctlidx 0: cfgCtl 0x12 pCtlMode 0x02 ctlIndex 0x10 chan 2417 chanctl 0x12
LOOP-Ctlidx 1: cfgCtl 0x12 pCtlMode 0x02 ctlIndex 0x16 chan 2417 chanctl 0x12
LOOP-Ctlidx 2: cfgCtl 0x12 pCtlMode 0x02 ctlIndex 0x18 chan 2417 chanctl 0x12
LOOP-Ctlidx 3: cfgCtl 0x12 pCtlMode 0x02 ctlIndex 0x11 chan 2417 chanctl 0x12
LOOP-Ctlidx 4: cfgCtl 0x12 pCtlMode 0x02 ctlIndex 0x12 chan 2417 chanctl 0x12
MATCH-EE_IDX 4: ch 2417 is2 1 2xMinEdge 36 chainmask 7 chains 3
SEL-Min ctlMode 1 pCtlMode 2 2xMaxEdge 36 sP 44 minCtlPwr 36
LOOP-Mode ctlMode 2 < 3, isHt40CtlMode 0, EXT_ADDITIVE 0
LOOP-Ctlidx 0: cfgCtl 0x12 pCtlMode 0x05 ctlIndex 0x10 chan 2417 chanctl 0x12
LOOP-Ctlidx 1: cfgCtl 0x12 pCtlMode 0x05 ctlIndex 0x16 chan 2417 chanctl 0x12
LOOP-Ctlidx 2: cfgCtl 0x12 pCtlMode 0x05 ctlIndex 0x18 chan 2417 chanctl 0x12
LOOP-Ctlidx 3: cfgCtl 0x12 pCtlMode 0x05 ctlIndex 0x11 chan 2417 chanctl 0x12
LOOP-Ctlidx 4: cfgCtl 0x12 pCtlMode 0x05 ctlIndex 0x12 chan 2417 chanctl 0x12
LOOP-Ctlidx 5: cfgCtl 0x12 pCtlMode 0x05 ctlIndex 0x15 chan 2417 chanctl 0x12
MATCH-EE_IDX 5: ch 2417 is2 1 2xMinEdge 36 chainmask 7 chains 3
SEL-Min ctlMode 2 pCtlMode 5 2xMaxEdge 36 sP 44 minCtlPwr 36

6M OFDM 18.0 dBm | 9M OFDM 18.0 dBm | 12M OFDM 18.0 dBm | 18M OFDM 18.0 dBm
24M OFDM 18.0 dBm | 36M OFDM 17.0 dBm | 48M OFDM 15.0 dBm | 54M OFDM 13.0 dBm
1L CCK 19.0 dBm | 2L CCK 19.0 dBm | 2S CCK 19.0 dBm | 5.5L CCK 19.0 dBm
5.5S CCK 19.0 dBm | 11L CCK 19.0 dBm | 11S CCK 19.0 dBm | XR 18.0 dBm
HT20mc 0 18.0 dBm | HT20mc 1 18.0 dBm | HT20mc 2 18.0 dBm | HT20mc 3 18.0 dBm
HT20mc 4 18.0 dBm | HT20mc 5 17.0 dBm | HT20mc 6 13.0 dBm | HT20mc 7 12.0 dBm
HT40mc 0 0.0 dBm | HT40mc 1 0.0 dBm | HT40mc 2 0.0 dBm | HT40mc 3 0.0 dBm
HT40mc 4 0.0 dBm | HT40mc 5 0.0 dBm | HT40mc 6 0.0 dBm | HT40mc 7 0.0 dBm
Dup CCK 0.0 dBm | Dup OFDM 0.0 dBm | Ext CCK 0.0 dBm | Ext OFDM 0.0 dBm
2xMaxPowerLevel: 36 (HT20)

[cgervasi]

Hello,

What software are you using and do they take into account our power offset?

Thanks,

Mike

Do you have documentation on the power offset?

We are able to extract data from the card's EEPROM showing its maximum output power on all channels and data rates. As expected, higher data rates support less power. The highest power we're seeing at any frequency or data rate is 19dBm. Is that what we should be seeing?

Thanks,

CJ

[cgervasi]

Can anyone tell me whether it's normal for the CTL table in SR-71's EEPROM to report 19dBm as maximum power?

Thanks,

CJ

[UBNT-Mike.Ford]

Hello,

According to our hardware team, this is normal programming for this card. Sorry for the confusion.

THanks,

Mike

[cgervasi]

According to our hardware team, this is normal programming for this card. Sorry for the confusion.


How is the driver supposed to know how to set the output power for a particular frequency and datarate if it can't trust values in the CTL tables?

[cgervasi]

I was thinking further about what you said about it being normal for SR71 EEPROM values to be wrong.

Might these values refer to the maximum power you can get out of a single channel? The maximum output rating for the card is 24dBm. I imagine each channel, though, can only generate a third of that, 18dBm. In this case, the values aren't really wrong, and it is normal that I should only be able to set the card to 18dBm and measure 18dBm out of any one port.

[rajendra]

Hello,
I saw a mention of power offset here. is there some reference code or documentation about how to use this power offset in the driver?

Thanks
rajendra

[cgervasi]

Might these values refer to the maximum power you can get out of a single channel? The maximum output rating for the card is 24dBm. I imagine each channel, though, can only generate a third of that, 18dBm.

The card has 24dBm on a and g modes to, which don't support multiple transmit chains. So the PA must be able to get to 24dBm with sufficient linearity to support OFDM.

How do we configure the card to get to 24dBm?

[cgervasi]

Hello,
I saw a mention of power offset here. is there some reference code or documentation about how to use this power offset in the driver?

Thanks
rajendra

I have found out that EEPROM values have a 3dB offset, so 19dBm actually means 22dBm. I think the reason for the offset is that the MadWiFi driver does not support high power values. I do not know why the max power is 22dBm when that datasheet shows 24dBm.

I will post more info as I get it.

[UBNT-Mike.Ford]

Hello,

I am attempting to get more info for you as well.

Thanks,

Mike

[cgervasi]

I am attempting to get more info for you as well.


I have heard that the reason the card only goes up to 19+3=22dBm is that not all units go up to 24dBm. It varies from card to card.

Thanks for looking into this. What we really need is the key to getting the card up to max power with the Atheros driver. Right now it's not putting out much more than a SparkLAN card not marketed as high-power.

Our software contractor, TF1, does not know how to incorporate the 3dB offset into their code (using Atheros driver) to get to full power. It peaks out around 18 or 19 dBm. I think the driver is wrongly believing the values in EEPROM w/o taking into account an offset.